DVS for On-Chip Bus Designs Based on Timing Error Correction (2007)
Kaul, Himanshu, Sylvester, Dennis, Blaauw, David, Mudge, Trevor, Austin, Todd
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result...
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage (2007)
Bai, Robert, Kim, Nam-Sung, Kgil, Tae Ho, Sylvester, Dennis, Mudge, Trevor
In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache...
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage (2007)
Bai, Robert, Kim, Nam-Sung, Kgil, Tae Ho, Sylvester, Dennis, Mudge, Trevor
In this paper, we investigate the impact of T_{ox} and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache...
DVS for On-Chip Bus Designs Based on Timing Error Correction (2007)
Kaul, Himanshu, Sylvester, Dennis, Blaauw, David, Mudge, Trevor, Austin, Todd
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching pattern. This can result...
Smart Register Files for High-Performance Microprocessors (2007)
Postiff, Matthew A., Mudge, Trevor
This report examines how the compiler can more efficiently use a large number of processor registers. The placement of data items into registers, called register allocation, is known to be one of the...
Wireless Networks 8, 507--520, 2002 (2003)
Krisztin Flautner, Steve Reinhardt, Trevor Mudge
The emphasis on processors that are both low power and high performance has resulted in the incorporation of dynamic voltage scaling into processor designs. This feature allows one to make fine...
Matt Postiff, Gary Tyson, Trevor Mudge
A growing number of studies have explored the use of trace caches as a mechanism to increase instruction fetch bandwidth. The trace cache is a memory structure that stores statically non-contiguous...
Automatic Performance Setting for Dynamic Voltage Scaling (2002)
Flautner, Krisztián, Reinhardt, Steve, Mudge, Trevor
The emphasis on processors that are both low power and high performance has resulted in the incorporation of dynamic voltage scaling into processor designs. This feature allows one to make fine...
Low-Energy Data Cache Using Sign Compression and (2002)
Nam Sung Kim, Todd Austin, Trevor Mudge
Cache accesses consume a significant portion of total energy dissipation in modern microprocessors. In this paper, we introduce a new technique for data cache energy reduction, which exploits the...
A Design Language for Modular Asynchronous Control Structures. (2002)
A design language for asynchronous digital systems is presented. The language translates onto a set of asynchronous logic modules, to form the control structure of a digital system. The behavior of...
Integrating Superscalar Processor Components to Implement Register Caching (2001)
Matthew Postiff, David Greene, Steven Raasch, Trevor Mudge
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical...
Power: A First Class Design Constraint for Future Architectures (2001)
In many mobile and embedded environments power is already the leading design constraint. This paper argues that power will also be a limiting factor in general purpose high-performance computers. It...
High-Performance DRAMs in Workstation Environments (2001)
Cuppu, Vinodh, Jacob, Bruce, Davis, Brian, Mudge, Trevor
This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations...
High-Performance DRAMs in Workstation Environments (2001)
Cuppu, Vinodh, Jacob, Bruce, Davis, Brian, Mudge, Trevor
This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations...
Integrating Superscalar Processor Components to Implement Register Caching (2001)
Matthew Postiff, David Greene, Steven Raasch, Trevor Mudge
A large logical register file is important to allow effective compiler transformations or to provide a windowed space of registers to allow fast function calls. Unfortunately, a large logical...
Uniprocessor Virtual Memory Without TLBs (2001)
We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in...
Uniprocessor Virtual Memory Without TLBs (2001)
We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in...
Improving Code Density Using Compression Techniques (2001)
Charles Lefurgy, Peter Bird, I-cheng Chen, Trevor Mudge
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of...
The Store-Load Address Table and Speculative Register Promotion (2000)
Matthew Postiff, David Greene, Trevor Mudge
Register promotion is an optimization that allocates a value to a register for a region of its lifetime where it is provably not aliased. Conventional compiler analysis cannot always prove that a...
The New DRAM Interfaces: SDRAM, RDRAM and Variants (2000)
Brian Davis, Bruce Jacob, Trevor Mudge
. For the past two decades, developments in DRAM technology, the primary technology for the main memory of computers, have been directed towards increasing density. As a result 256 M-bit memory chips...
DDR2 and Low Latency Variants (2000)
Brian Davis, Trevor Mudge, Bruce Jacob
This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the...
DDR2 and Low Latency Variants (2000)
Davis, Brian, Mudge, Trevor, Jacob, Bruce, Cuppu, Vinodh
This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the...
DDR2 and Low Latency Variants (2000)
Davis, Brian, Mudge, Trevor, Jacob, Bruce, Cuppu, Vinodh
This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the...
Performance Limits of Trace Caches (1999)
Matt Postiff, Gary Tyson, Trevor Mudge
A growing number of studies have explored the use of trace caches as a mechanism to increase instruction fetch bandwidth. The trace cache is a memory structure that stores statically non-contiguous...
Evaluation of a High Performance Code Compression Method (1999)
Charles Lefurgy, Eva Piccininni, Trevor Mudge
Compressing the instructions of an embedded program is important for cost-sensitive lowpower control-oriented embedded computing. A number of compression schemes have been proposed to reduce program...
Smart Register Files for High-Performance Microprocessors (1999)
Matthew A. Postiff, Trevor Mudge
This report examines how the compiler can more efficiently use a large number of processor registers. The placement of data items into registers, called register allocation, is known to be one of the...
Timing Verification of Sequential Dynamic Circuits (1999)
David Van Campenhout, Student Member, Trevor Mudge, Karem A. Sakallah
This paper addresses static timing verification for sequential circuits implemented in a mix of static and dynamic logic. We restrict our focus to regular domino logic and footless domino logic, a...
A Performance Comparison of Contemporary DRAM Architectures (1999)
Cuppu, Vinodh, Jacob, Bruce, Davis, Brian, Mudge, Trevor
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study...
A Performance Comparison of Contemporary DRAM Architectures (1999)
Cuppu, Vinodh, Jacob, Bruce, Davis, Brian, Mudge, Trevor
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study...
A Parallel Genetic Algorithm for Multiobjective Microprocessor Design (1999)
Timothy J. Stanley, Trevor Mudge
The microprocessor chip designer must solve the problem of partitioning millions of transistors into an arbitrary number of hardware structures within a finite chip area toward achieving...
High-Level Design Verification of. . . (1999)
David Van Campenhout, Hussain Al-asaad, John P. Hayes, Trevor Mudge, Richard B. Brown
A design verification methodology for microprocessor hardware based on modeling errors and generating simulation vectors for the modeled...
Code Compression for DSP (1998)
Previous works have proposed adding compression techniques to a variety of architectural styles to reduce instruction memory requirements. It is not immediately clear how these results apply to DSP...
Jim Pierce, Michael D. Smith, Trevor Mudge
Execution) is a tracing system developed by Larus and Ball which is incorporated as part of the Gnu C compiler [3]. Its goal is to generate very small traces which can be saved and then reused for...
David Van Campenhout, Hussain Al-asaad, John P. Hayes, Trevor Mudge, Richard B. Brown
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission...
High-Level Test Generation for Design Verification of Pipelined Microprocessors (1998)
David Van Campenhout, Trevor Mudge, John P. Hayes
This paper addresses test generation for design verification of pipelined microprocessors. We describe a highlevel model for testing pipelined microprocessors, which exposes high-level knowledge that...
A high level simulator integrated with the Mirv compiler (1998)
A program's execution profile is an increasingly important source of information for optimizations. Along with its use for high-level optimizations, profile information can be used to take advantage...
Power Analyzer for Pocket Computing (PAPC) (1998)
Mudge, Trevor, Kim, Nam S., Ringenberg, Jeffrey, Kgil, Taeho
Under this contract researchers at the Universities of Michigan and Colorado have developed an innovative and practical power evaluation tool, Power Analyzer, suitable for calculating power...
High-Level Design Verification of Microprocessors via Error Modeling (1998)
H. Al-asaad, D. Van Campenhout, J. P. Hayes, T. Mudge, Hussain Al-asaad, David Van Campenhout, ...
A project is under way at the University of Michigan to develop a design verification methodology for microprocessor hardware based on modeling design errors and generating simulation vectors for the...
High-Level Design Verification of Microprocessors via Error Modeling (1998)
David Van Campenhout, Hussain Al-asaad, John P. Hayes, Trevor Mudge, Richard B. Brown
this paper was presented in [4] at the 1997 IEEE International High Level Design Validation and Test Workshop, Oakland, California, November 14-15, 1997
Improving Code Density Using Compression Techniques (1998)
Charles Lefurgy, Peter Bird, I-cheng Chen, Trevor Mudge
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of...
Virtual Memory: Issues of Implementation (1998)
The authors introduce basic virtual-memory technologies and then compare memory-management designs in three commercial microarchitectures. They show the diversity of virtual-memory support and, by...
Virtual Memory: Issues of Implementation (1998)
The authors introduce basic virtual-memory technologies and then compare memory-management designs in three commercial microarchitectures. They show the diversity of virtual-memory support and, by...
Rich Brown, John Hayes, Trevor Mudge (1998)
Rich Brown, John Hayes, Trevor Mudge
This report discusses our work with an emulator based on field programmable gate array technology. This technology has made possible the construction of hardware emulators capable of emulating...
Notes on Calculating Computer Performance (1998)
This report explains what it means to characterize the performance of a computer, and which methods are appropriate and inappropriate for the task. The most widely used metric is the performance on...
The Trading Function in Action (1998)
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
Virtual Memory in Contemporary Microprocessors (1998)
THIS SURVEY OF SIX COMMERCIAL MEMORY-MANAGEMENT DESIGNS DESCRIBES HOW EACH PROCESSOR ARCHITECTURE SUPPORTS THE COMMON FEATURES OF VIRTUAL MEMORY: ADDRESS SPACE PROTECTION, SHARED MEMORY, AND LARGE...
Virtual Memory in Contemporary Microprocessors (1998)
THIS SURVEY OF SIX COMMERCIAL MEMORY-MANAGEMENT DESIGNS DESCRIBES HOW EACH PROCESSOR ARCHITECTURE SUPPORTS THE COMMON FEATURES OF VIRTUAL MEMORY: ADDRESS SPACE PROTECTION, SHARED MEMORY, AND LARGE...
Improving Code Density Using Compression Techniques (1997)
Charles Lefurgy, Peter Bird, I-cheng Chen, Trevor Mudge
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of...
The Trading Function in Action (1997)
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
Timing Verification of Sequential Domino Circuits (1997)
David Van Campenhout, Trevor Mudge, Karem A. Sakallah
Two methods are presented for static timing verification of sequential circuits implemented as a mix of static and domino logic. Constraints for proper operation of domino gates are derived. An...
Support for Nomadism in a Global Environment (1997)
. The goal of nomadic computing transcends simply making one's environment portable; mobile users require the ability to communicate with local servers despite location and to obtain local services...
Improving Code Density Using Compression Techniques (1997)
Charles Lefurgy, Peter Bird, I-cheng Chen, Trevor Mudge
We propose a method for compressing programs in embedded processors where instruction memory size dominates cost. A post-compilation analyzer examines a program and replaces common sequences of...
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
Rich Brown, John Hayes, Trevor Mudge (1997)
Rich Brown, John Hayes, Trevor Mudge
This report discusses our work with an emulator based on field programmable gate array technology. This technology has made possible the construction of hardware emulators capable of emulating...
Improving Data Cache Performance By Pre-Executing Instructions Under a Cache Miss. (1997)
this paper we propose and evaluate a technique that improves first level data cache performance by pre-executing future instructions under a data cache miss. We show that these preexecuted...
Timing Verification of Sequential Domino Circuits (1997)
D. Van Campenhout, T. Mudge, K. Sakallah, David Van Campenhout, Trevor Mudge, Karem A. Sakallah
Two methods are presented for static timing verification of sequential circuits implemented as a mix of static and domino logic. Constraints for proper operation of domino gates are derived. An...
Wrong-Path Instruction Prefetching (1997)
Instruction cache misses can severely limit the performance of both superscalar processors and high speed sequential machines. Instruction prefetch algorithms attempt to reduce the performance...
Software-Managed Address Translation (1997)
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple...
Software-Managed Address Translation (1997)
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple...
Wrong-Path Instruction Prefetching (1997)
Instruction cache misses can severely limit the performance of both superscalar processors and high speed sequential machines. Instruction prefetch algorithms attempt to reduce the performance...
Timing Analysis of Domino Logic (1996)
David Van Campenhout, Trevor Mudge, Karem Sakallah
High performance microprocessors employ various advanced circuit techniques to obtain the required speed. Critical sections of the design are often implemented in domino logic, a popular style of...
Faster Static Timing Analysis via Bus Compression (1996)
David Van Campenhout, Trevor Mudge
Static timing analysis is used extensively in the design of high-performance processors. In this paper we present a method which transforms the circuit graph used by timing analysis algorithms to a...
Support for Nomadism in a Global Environment (1996)
The goal of nomadic computing transcends simply making one's environment portable; mobile users require the ability to communicate with local servers despite location and to obtain local services...
The Trading Function in Action (1996)
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
The Trading Function in Action (1996)
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
Memory Management Hardware, and its Support for Operating Systems (1996)
. This survey compares and contrasts the memory management designs of six commercial microarchitectures in the context of today's operating system requirements, which include such features as...
Design Tradeoffs for Software-Managed TLBs (1996)
Richard Uhlig, David Nagle, Tim Stanley, Trevor Mudge, Sechrest Richard Brown
this paper appeared in the Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, May 1993. Authors' address: Department of Electrical Engineering and Computer...
A Microarchitectural Performance Evaluation of a 3.2 Gbyte/s Microprocessor Bus (1995)
Tim Stanley, Michael Upton, Patrick Sherhart, Trevor Mudge, Richard Brown
Several architectural innovations intended to reduce access latency and improve overall throughput increase system bandwidth requirements. Bandwidth scales with clock speed, and can be regarded as an...
A Microarchitectural Performance Evaluation of a 3.2 Gbyte/s Microprocessor Bus (1995)
Tim Stanley, Michael Upton, Patrick Sherhart, Trevor Mudge, Richard Brown
Several architectural innovations intended to reduce access latency and improve overall throughput increase system bandwidth requirements. Bandwidth scales with clock speed, and can be regarded as an...
A Parallel Genetic Algorithm for Multiobjective Microprocessor Design (1995)
Timothy J. Stanley, Trevor Mudge
The microprocessor chip designer must solve the problem of partitioning millions of transistors into an arbitrary number of hardware structures within a finite chip area toward achieving...
Systematic Objective-driven Computer Architecture Optimization (1995)
Timothy J. Stanley, Trevor Mudge
Computer designers now have more transistors and architectural alternatives than at any time. Computer-aided design tools automate much of the physical design process. However, few tools have been...
Design Tradeoffs for Software-Managed TLBs (1995)
Richard Uhlig, David Nagle, Tim Stanley, Trevor Mudge, Sechrest Richard Brown
this paper appeared in the Proceedings of the 20th Annual International Symposium on Computer Architecture, San Diego, May 1993. Authors' address: Department of Electrical Engineering and Computer...
IDtrace - A Tracing Tool for i486 Simulation (1994)
This technical report describes IDtrace, a program that produces execution traces for ix86 instruction set architectures using late-code modification. IDtrace provides a low cost method for producing...
lDtrace --- A Tracing Tool for i486 Simulation (1994)
This technical report describes IDtrace, a program that produces execution traces for ix86 instruction set architectures using late-code modification. IDtrace provides a low cost method for producing...