Numerically Stable Algorithms for Inversion of Block Tridiagonal and Banded Matrices (2007)
Jain, Jitesh, Li, Hong, Cauley, Stephen, Koh, Cheng-Kok, Balakrishnan, Venkataramanan
We provide a new representation for the inverse of block tridiagonal and banded matrices. The new representation is shown to be numerically stable over a variety of block tridiagonal matrices, in...
On Improving Recursive Bipartitioning-Based Placement (2003)
We present an improved partitioning-based placement tool in terms of the half-perimeter wirelength. In contrast to placement tools that exploit white spaces to reduce the routing congestion, our...
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Decoupling Capacitance Allocation for Power Supply (2003)
Shiyou Zhao, Kaushik Roy, Cheng-kok Koh
We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. Decoupling capacitance budgets for the circuit modules are calculated based on...
Jason Cong, Lei He, Kei-yong Khoo, Cheng-kok Koh, Zhigang Pan
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
Performance Analysis and Efficient Implementation of Latency Insensitive Systems (2003)
This paper studies the performance of latency insensitive systems with limited queue size, in contrast with previous studies that assumed unlimited queue size. We obtain a tight theoretical...
Interconnect Planning with Local Area Constrained Retiming (2003)
We present a framework that considers global routing, repeater insertion, and flip-flop relocation for early interconnect planning. We formulate the interconnect retiming and flip-flop placement...
Performance optimization of VLSI interconnect layout (2003)
Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden
This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and...
Non-Crossing Ordered BDD for Physical Synthesis of Regular Circuit Structure (2003)
In this paper, we propose a novel compact BDD structure, called Non-crossing ordered BDD (NCOBDD), that can be mapped directly to a regular circuit structure. Compared with other BDD-based regular...
Interconnect Sizing and Spacing with Consideration of Coupling Capacitance (2002)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang (david Pan
This paper studies interconnect sizing and spacing (ISS) problem with consideration of coupling capacitance for performance optimization of single or multiple critical nets. We introduce the...
Flip-Flop and Repeater Insertion for Early Interconnect Planning (2002)
Ruibing Lu, Guoan Zhong, Cheng-kok Koh, Kai-yuan Chao
We present a unified framework that considers flipflop and repeater insertion and the placement of flipflop /repeater blocks during RT or higher level design. We introduce the concept of independent...
Manhattan or Non-Manhattan? A Study of Alternative VLSI Routing Architectures (2002)
Cheng-kok Koh, Patrick H. Madden
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the interconnect problem...
On-chip Interconnect Modeling by Wire Duplication (2002)
Zhong, Guoan, Koh, Cheng-Kok, Roy, Kaushik
In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique uses the original inductance to exploit the sparsity of the L
Simultaneous Buffer and Wire Sizing for Performance and Power Optimization (2001)
Jason Cong, Cheng-kok Koh, Kwok-shing Leung
In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation...
Power Minimization by Simultaneous Dual-V Assignment and Gate-sizing (2001)
Liqiong Wei, Kaushik Roy, Cheng-kok Koh
Gate-sizing is an effective technique to optimize CMOS circuits for dynamic power dissipation and performance while dual-V th (threshold voltage) CMOS is ideal for leakage power reduction in low...
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional (2001)
Rongtian Zhang, Kaushik Roy, Cheng-kok Koh, David B. Janes
Dimensional (3-D) integration offers numerous advantages over conventional structures. Double-gate (DG) transistors can be fabricated for better device characteristics, and multiple device layers can...
Rongtian Zhang, Kaushik Roy, Cheng-kok Koh, David B. Janes
D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into...
Rongtian Zhang, Kaushik Roy, Cheng-kok Koh, David B. Janes
D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into...
Global Interconnect Sizing And Spacing With Consideration Of Coupling Capacitance (2001)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Minimum-Cost Bounded-Skew Clock Routing (2001)
In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm constructs a bounded-skew tree (BST) in two steps: (i) a...
Manhattan or Non-Manhattan? A Study of Alternative VLSI Routing Architectures (2001)
Cheng-kok Koh, Patrick H. Madden
Circuit interconnect has become a substantial obstacle in the design of high performance systems. In this paper we explore a new routing paradigm that strikes at the root of the interconnect problem...
Frequency Domain Analysis of Switching Noise on Power Supply Network (2001)
Shiyou Zhao, Kaushik Roy, Cheng-kok Koh
In this paper, we propose an approach for the analysis of power supply noise in the frequency domain for power/ground (P/G) networks of tree topologies. We model the P/G network as a linear time...
A Twisted-Bundle Layout Structure for Minimizing Inductive Coupling Noise (2001)
Guoan Zhong, Cheng-kok Koh, Kaushik Roy
In this paper, we propose a novel twisted-bundle layout structure for minimizing inductive coupling noise. In this structure, we create several routing regions and re-order the routing of nets in...
Performance Optimization of VLSI Interconnect Layout (2001)
Jason Cong, Lei He, Cheng-kok Koh, Patrick H. Madden
This paper presents a comprehensive survey of existing techniques for interconnect optimizationduring the VLSI physical design process, with emphasis on recent studies on interconnect design and...
Interconnect Layout Optimization Under Higher-Order RLC Model (2001)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Simultaneous Driver and Wire Sizing for Performance and Power Optimization (2001)
In this paper, we study the simultaneous driver and wire sizing (SDWS) problem under two objective functions: (i) delay minimization only, or (ii) combined delay and power dissipation minimization....
Routability-Driven Repeater Block Planning for Interconnect-Centric Floorplanning (2001)
Interconnect-centric Floorplanning, Probir Sarkar, Vivek Sundararaman, Cheng-kok Koh
In this paper we present a repeater block planning algorithm for interconnect-centric floorplanning. We introduce the concept of independent feasible regions for repeaters and derive an analytical...
Interconnect Design for Deep Submicron ICs (2001)
Jason Cong, Lei He, Kei-yong Khoo, Cheng-kok Koh, Zhigang Pan
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
High-Performance Low-Power Carry Select Adder using Dual Transition Skewed Logic (2001)
Woopyo Jeong, Kaushik Roy, Cheng-kok Koh
In this paper, we present a low power and high performance Carry Select Adder (CSA) using Dual Transition Skewed Logic (DTSL) suitable for high noise immunity. We compared DTSL Carry Select Adder...
Decoupling Capacitance Allocation for Power Supply Noise Suppression (2001)
Shiyou Zhao, Kaushik Roy, Cheng-kok Koh
We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. Decoupling capacitance budgets for the circuit modules are calculated based on...
Repeater Block Planning under Simultaneous Delay and Transition Time Constraints (2001)
We present a solution to the problem of repeater block planning under both delay and signal transition time constraints for a given floorplan. Previous approaches have considered only meeting the...
Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-kok Koh, Kaushik Roy
In very high performance designs, dynamic circuits, such as Domino Logic, are used because of their high speed. Skewed logic circuits can be used to achieve designs having performance comparable to...
Shiyou Zhao, Kaushik Roy, Cheng-kok Koh
In this paper, we propose an event-driven simulation based approach to estimate the worst case IR drop and L di dt inductive noise on the power supply network. Resistive and inductive parasitics on...
Stochastic Wire-Length and Delay Distributions of 3-Dimensional (2001)
Rongtian Zhang, Kaushik Roy, Cheng-kok Koh, David B. Janes
D technology promises higher integration density and lower interconnection complexity and delay. At present, however, not much work on circuit applications has been done due to lack of insight into...
Wiresizing with Driver Sizing for Performance and Power Optimization (2001)
Jason Cong, Cheng-kok Koh, Kwok-shing Leung
In this paper, we study the effect of wiresizing with driver sizing on performance and power optimization. Our study showed that wiresizing is an effective method to reduce interconnect delay....
Exact Closed Form Fom~ulafo r Partial Mutual Inductances of On-Chip Interconnects (2001)
In this paper, we propose a new exact closed form mutual inductance equation for on-chip interconnects. We express the mutual inductance between two parallel rectangular conductors as a weighted sum...
Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration (2001)
Rongtian Zhang, Kaushik Roy, Cheng-kok Koh, David B. Janes
Dimensional (3-D) integration offers numerous advantages over conventional structures. Double-gate (DG) transistors can be fabricated for better device characteristics, and multiple device layers can...
Repeater Block Planning under Simultaneous Delay and (2001)
We present a solution to the problem of repeater block planning under both delay and signal transition time constraints for a given floorplan. Previous approaches have considered only meeting the...
Interconnect Design for Deep Submicron ICs (2000)
Jason Cong, Zhigang Pan, Lei He, Cheng-kok Koh, Kei-yong Khoo
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
Efficient Balance-and-Truncate Model Reduction for Large Scale Systems (2000)
Balakrishnan, Venkataramanan, Su, Qing, Koh, Cheng-Kok
We present efficient implement at ions of the balanceand- truncate model reduction technique for large-scale systems. The key observation that distinguishes our approach is that Krylov subspace...
UST/DME: A Clock Tree Router For General Skew Constraints (2000)
In this paper, we propose new approaches for solving the usefulskew tree (UST) routing problem [17]: Clock routing subject to general skew constraints. The clock layout synthesis engine of our UST...
Frequency Domain Analysis of Switching Noise on Power Supply Network (2000)
Zhao, Shiyou, Roy, Kaushik, Koh, Cheng-Kok
In this paper, we propose an approach for the analysis of power supply noise in the frequency domain. Power supply network is modeled as a linear time invariant (LTI) system comprising of the...
Bounded-Skew Clock and Steiner Routing (1999)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh, C. -w, Albert Tsao
this paper we study the BST problem under both the pathlength (linear) and Elmore delay models [Elmore 1948]. We propose the new BST/DME algorithm which, similar to the DME construction of a...
Bounded-Skew Clock and Steiner Routing (1999)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
this paper we study the BST problem under both the pathlength (linear) and Elmore delay models [Elmore 1948]. We propose the new BST/DME algorithm which, similar to the DME construction of a...
Manhattan or Non-Manhattan? - A Study of Alternative VLSI Routing Architectures (1999)
Koh, Cheng-Kok, Madden, Patrick H.
performance systems. .4 large portion of system delay, as well as power consumption and electrical noise, can be attributed to the interconnect. To adldress these challenges, much work has been done...
Interconnect Layout Optimization Under Higher-Order RLC Model (1998)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance (1998)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Interconnect Layout Optimization Under Higher-Order RLC Model (1998)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance (1998)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Global Interconnect Sizing And Spacing With Consideration Of Coupling Capacitance (1998)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Interconnect Design for Deep Submicron ICs (1998)
Jason Cong, Lei He, Kei-yong Khoo, Cheng-kok Koh, Zhigang Pan
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
Global Interconnect Sizing And Spacing With Consideration Of Coupling Capacitance (1998)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Interconnect Design for Deep Submicron ICs (1998)
Jason Cong, Lei He, Kei-yong Khoo, Cheng-kok Koh, Zhigang Pan
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance (1998)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
VLSI interconnect layout optimization / (1998)
Thesis (Ph. D.)--University of California, Los Angeles, 1998.
Interconnect Layout Optimization Under Higher-Order RLC Model (1997)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Interconnect Layout Optimization Under Higher-Order RLC Model (1997)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance (1997)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Bounded-Skew Clock and Steiner Routing (1997)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission...
algorithm, extends the DME algorithm for exact zero-skew trees via the concept of a (1997)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission...
Interconnect Design for Deep Submicron ICs (1997)
Jason Cong, Lei He, Kei-yong Khoo, Cheng-kok Koh, Zhigang Pan
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
Interconnect Layout Optimization Under Higher-Order RLC Model (1997)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Interconnect Layout Optimization Under Higher-Order RLC Model (1997)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Interconnect Design for Deep Submicron ICs (1997)
Jason Cong, Lei He, Kei-yong Khoo, Cheng-kok Koh, Zhigang Pan
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
Global Interconnect Sizing And Spacing With Consideration Of Coupling Capacitance (1997)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Interconnect Layout Optimization Under Higher-Order RLC Model (1997)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Interconnect Design for Deep Submicron ICs (1997)
Jason Cong, Lei He, Kei-yong Khoo, Cheng-kok Koh, Zhigang Pan
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
algorithm, extends the DME algorithm for exact zero-skew trees via the concept of a (1997)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission...
Global Interconnect Sizing And Spacing With Consideration Of Coupling Capacitance (1997)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Interconnect Layout Optimization Under Higher-Order RLC Model (1997)
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monotone signal response....
Global Interconnect Sizing And Spacing With Consideration Of Coupling Capacitance (1997)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
Interconnect Design for Deep Submicron ICs (1997)
Jason Cong, Lei He, Kei-yong Khoo, Cheng-kok Koh, Zhigang Pan
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...
algorithm, extends the DME algorithm for exact zero-skew trees via the concept of a (1997)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission...
Global Interconnect Sizing And Spacing With Consideration Of Coupling Capacitance (1997)
Jason Cong, Lei He, Cheng-kok Koh, Zhigang Pan
This paper presents an efficient approach to perform global interconnect sizing and spacing (GISS) for multiple nets to minimize interconnect delays with consideration of coupling capacitance, in...
algorithm, extends the DME algorithm for exact zero-skew trees via the concept of a (1997)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission...
Bounded-Skew Clock and Steiner Routing Under Elmore Delay (1997)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
: We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We present two approaches to construct bounded-skew routing trees: (i) the Boundary Merging and Embedding...
algorithm, extends the DME algorithm for exact zero-skew trees via the concept of a (1997)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
ing with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works, requires prior specific permission...
Bounded-Skew Clock and Steiner Routing Under Elmore Delay (1997)
Jason Cong, Andrew B. Kahng, Cheng-kok Koh
: We study the minimum-cost bounded-skew routing tree problem under the Elmore delay model. We present two approaches to construct bounded-skew routing trees: (i) the Boundary Merging and Embedding...
Interconnect Design for Deep Submicron ICs (1997)
Jason Cong, Zhigang Pan, Lei He, Cheng-kok Koh, Kei-yong Khoo
Interconnect has become the dominating factor in determining circuit performance and reliability in deep submicron designs. In this embedded tutorial, we first discuss the trends and challenges of...