Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling (2007)
Ganesh, Brinda, Jaleel, Aamer, Wang, David, Jacob, Bruce
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an alternate...
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling (2007)
Ganesh, Brinda, Jaleel, Aamer, Wang, David, Jacob, Bruce
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an alternate...
Modeling Heterogeneous SoCs with SystemC: A Digital/MEMS Case Study (2006)
Varma, Ankush, Afridi, M. Yaqub, Akturk, Akin, Klein, Paul, Hefner, Allen R., Jacob, Bruce
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital parts of a system. This...
Modeling Heterogeneous SoCs with SystemC: A Digital/MEMS Case Study (2006)
Varma, Ankush, Afridi, M. Yaqub, Akturk, Akin, Klein, Paul, Hefner, Allen R., Jacob, Bruce
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital parts of a system. This...
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs) (2006)
The effects of the general-purpose precise interrupt mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors handle interrupts precisely,...
In-Line Interrupt Handling and Lock-Up Free Translation Lookaside Buffers (TLBs) (2006)
The effects of the general-purpose precise interrupt mechanisms in use for the past few decades have received very little attention. When modern out-of-order processors handle interrupts precisely,...
Jaleel, Aamer, Mattina, Matthew, Jacob, Bruce
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and discover meaningful...
Jaleel, Aamer, Mattina, Matthew, Jacob, Bruce
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and discover meaningful...
DRAMsim: A Memory System Simulator (2005)
Wang, David, Ganesh, Brinda, Tuaycharoen, Nuengwong, Baynes, Kathleen, Jaleel, Aamer, Jacob, Bruce
As memory accesses become slower with respect to the processor and consume more power with increasing memory size, the focus of memory performance and power consumption has become increasingly...
DRAMsim: A Memory System Simulator (2005)
Wang, David, Ganesh, Brinda, Tuaycharoen, Nuengwong, Baynes, Kathleen, Jaleel, Aamer, Jacob, Bruce
As memory accesses become slower with respect to the processor and consume more power with increasing memory size, the focus of memory performance and power consumption has become increasingly...
BioBench: A Benchmark Suite of Bioinformatics Applications (2005)
Albayraktaroglu, Kursad, Jaleel, Aamer, Wu, Xue, Franklin, Manoj, Jacob, Bruce, Tseng, Chau-Wen, ...
Recent advances in bioinformatics and the significant increase in computational power available to researchers have made it possible to make better use of the vast amounts of genetic data that has...
BioBench: A Benchmark Suite of Bioinformatics Applications (2005)
Albayraktaroglu, Kursad, Jaleel, Aamer, Wu, Xue, Franklin, Manoj, Jacob, Bruce, Tseng, Chau-Wen, ...
Recent advances in bioinformatics and the significant increase in computational power available to researchers have made it possible to make better use of the vast amounts of genetic data that has...
The use of large instruction windows coupled with aggressive out-of order and prefetching capabilities has provided significant improvements in processor performance. In this paper, we quantify the...
The use of large instruction windows coupled with aggressive out-of order and prefetching capabilities has provided significant improvements in processor performance. In this paper, we quantify the...
TERPS: The Embedded Reliable Processing System (2005)
Wang, Hongxia, Rodriguez, Samuel, Dirik, Cagdas, Gole, Amol, Chan, Vincent, Jacob, Bruce
TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TERPS tolerates EMI by periodically...
Instruction-Level Power Dissipation in the Intel XScale Embedded Microprocessor (2005)
Varma, Ankush, Debes, Eric, Kozintsev, Igor, Jacob, Bruce
We present an instruction-level power dissipation model of the Intel XScale R° microprocessor. The XScale implements the ARMTMISA, but uses an aggressive microarchitecture and a SIMD Wireless...
TERPS: The Embedded Reliable Processing System (2005)
Wang, Hongxia, Rodriguez, Samuel, Dirik, Cagdas, Gole, Amol, Chan, Vincent, Jacob, Bruce
TERPS is a fault-tolerant computer design that significantly reduces the threat of electromagnetic interference (EMI), using hardware checkpoint/rollback-recovery. TERPS tolerates EMI by periodically...
Instruction-Level Power Dissipation in the Intel XScale Embedded Microprocessor (2005)
Varma, Ankush, Debes, Eric, Kozintsev, Igor, Jacob, Bruce
We present an instruction-level power dissipation model of the Intel XScale R° microprocessor. The XScale implements the ARMTMISA, but uses an aggressive microarchitecture and a SIMD Wireless...
Radio Frequency Effects on the Clock Networks of Digital Circuits (2004)
Wang, Hongxia, Dirik, Cagdas, Rodriguez, Samuel V., Gole, Amol V., Jacob, Bruce
Radio frequency interference (RFI) can have adverse effects on commercial electronics. Current properties of high performance integrated circuits (ICs), such as very small feature sizes, high clock...
Radio Frequency Effects on the Clock Networks of Digital Circuits (2004)
Wang, Hongxia, Dirik, Cagdas, Rodriguez, Samuel V., Gole, Amol V., Jacob, Bruce
Radio frequency interference (RFI) can have adverse effects on commercial electronics. Current properties of high performance integrated circuits (ICs), such as very small feature sizes, high clock...
Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs (2004)
Iyer, Bharath, Srinivasan, Sadagopan, Jacob, Bruce
VLIW architecture based DSPs have become widespread due to the combined benefits of simple hardware and compiler-extracted instruction-level parallelism. However, the VLIW instruction set...
Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs (2004)
Iyer, Bharath, Srinivasan, Sadagopan, Jacob, Bruce
VLIW architecture based DSPs have become widespread due to the combined benefits of simple hardware and compiler-extracted instruction-level parallelism. However, the VLIW instruction set...
A Case for Studying DRAM Issues at the System Level (2003)
THE WIDENING GAP BETWEEN TODAY’S PROCESSOR AND MEMORY SPEEDS MAKES DRAM SUBSYSTEM DESIGN AN INCREASINGLY IMPORTANT PART OF COMPUTER SYSTEM DESIGN. IF THE DRAM RESEARCH COMMUNITY WOULD FOLLOW THE...
A Case for Studying DRAM Issues at the System Level (2003)
THE WIDENING GAP BETWEEN TODAY’S PROCESSOR AND MEMORY SPEEDS MAKES DRAM SUBSYSTEM DESIGN AN INCREASINGLY IMPORTANT PART OF COMPUTER SYSTEM DESIGN. IF THE DRAM RESEARCH COMMUNITY WOULD FOLLOW THE...
High-Performance DRAMs in Workstation Environments (2001)
Cuppu, Vinodh, Jacob, Bruce, Davis, Brian, Mudge, Trevor
This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations...
High-Performance DRAMs in Workstation Environments (2001)
Cuppu, Vinodh, Jacob, Bruce, Davis, Brian, Mudge, Trevor
This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated in a small system organization. These small-system organizations...
Given a fixed CPU architecture and a fixed DRAM timing specification, there is still a large design space for a DRAM system organization. Parameters include the number of memory channels, the...
Given a fixed CPU architecture and a fixed DRAM timing specification, there is still a large design space for a DRAM system organization. Parameters include the number of memory channels, the...
Uniprocessor Virtual Memory Without TLBs (2001)
We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in...
Uniprocessor Virtual Memory Without TLBs (2001)
We present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in...
The Performance and Energy Consumption of Embedded Real-Time Operating Systems (2000)
Baynes, Kathleen, Collins, Chris, Fiterman, Eric, Smit, Christine, Zhang, Tiebing, Jacob, Bruce
This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs...
The Performance and Energy Consumption of Embedded Real-Time Operating Systems (2000)
Baynes, Kathleen, Collins, Chris, Fiterman, Eric, Smit, Christine, Zhang, Tiebing, Jacob, Bruce
This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs...
The New DRAM Interfaces: SDRAM, RDRAM and Variants (2000)
Brian Davis, Bruce Jacob, Trevor Mudge
. For the past two decades, developments in DRAM technology, the primary technology for the main memory of computers, have been directed towards increasing density. As a result 256 M-bit memory chips...
Jacob, Bruce, Bhattacharyya, S. S.
No abstract submitted. (UMIACS-TR-2000-60)
Jacob, Bruce, Bhattacharyya, S. S.
No abstract submitted. (UMIACS-TR-2000-60)
Jacob, Bruce, Bhattacharyya, Shuvra S.
This paper demonstrates the intractability of achieving statically predictable performance behavior with traditional cache organizations (i.e., the real-time cache problem) and describes a...
DDR2 and Low Latency Variants (2000)
Brian Davis, Trevor Mudge, Bruce Jacob
This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the...
DDR2 and Low Latency Variants (2000)
Davis, Brian, Mudge, Trevor, Jacob, Bruce, Cuppu, Vinodh
This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the...
DDR2 and Low Latency Variants (2000)
Davis, Brian, Mudge, Trevor, Jacob, Bruce, Cuppu, Vinodh
This paper describes a performance examination of the DDR2 DRAM architecture and the proposed cache-enhanced variants. These preliminary studies are based upon ongoing collaboration between the...
This paper presents initial results in a study of organization level parameters associated with the design of the primary memory system—the DRAM system beneath the lowest level of the cache...
This paper presents initial results in a study of organization level parameters associated with the design of the primary memory system—the DRAM system beneath the lowest level of the cache...
XMT-M: A Scalable Decentralized Processor (1999)
Efraim Berkovich, Joseph Nuzman, Manoj Franklin, Bruce Jacob, Uzi Vishkin
A defining challenge for research in computer science and engineering has been the ongoing quest for reducing the completion time of a single computation task. Even outside the parallel processing...
Hardware/Software Architectures for Real-Time Caching (1999)
There are two fundamental problems in guaranteeing cache performance for real-time embedded systems: conflict and capacity misses. Though fully associative caches would solve conflict misses, they...
Hardware/Software Architectures for Real-Time Caching (1999)
There are two fundamental problems in guaranteeing cache performance for real-time embedded systems: conflict and capacity misses. Though fully associative caches would solve conflict misses, they...
XMT-M: A Scalable Decentralized Processor (1999)
Efraim Berkovich, Joseph Nuzman, Manoj Franklin, Bruce Jacob, Uzi Vishkin
A defining challenge for research in computer science and engineering has been the ongoing quest for reducing the completion time of a single computation task. Even outside the parallel processing...
Hardware/Software Architectures for Real-Time Caching (1999)
Introduction Real-time embedded systems require guaranteed performance behavior because they interact with the real world. Today's embedded microprocessors are yesterday's high-performance desktop...
Hardware/Software Architectures for Real-Time Caching (1999)
Introduction Real-time embedded systems require guaranteed performance behavior because they interact with the real world. Today's embedded microprocessors are yesterday's high-performance desktop...
XMT-M: A Scalable Decentralized Processor (1999)
Berkovich, Efraim, Nuzman, Joseph, Franklin, Manoj, Jacob, Bruce, Vishkin, Uzi
A defining challenge for research in computer science and engineering has been the ongoing quest for reducing the completion time of a single computation task. Even outside the parallel processing...
XMT-M: A Scalable Decentralized Processor (1999)
Berkovich, Efraim, Nuzman, Joseph, Franklin, Manoj, Jacob, Bruce, Vishkin, Uzi
A defining challenge for research in computer science and engineering has been the ongoing quest for reducing the completion time of a single computation task. Even outside the parallel processing...
Cache Design for Embedded Real-Time Systems (1999)
Caches have long been a mechanism for speeding memory access and are popular in embedded hardware architectures from microcontrollers to core-based ASIC designs. However, caches are considered...
Cache Design for Embedded Real-Time Systems (1999)
Caches have long been a mechanism for speeding memory access and are popular in embedded hardware architectures from microcontrollers to core-based ASIC designs. However, caches are considered...
Stewart, David B., Jacob, Bruce
We have conceptualized a hardware-software codesign strategy for creating I/O interfacing hardware and real-time operating system device drivers for microcontrollers, enabling hardware independent...
A Performance Comparison of Contemporary DRAM Architectures (1999)
Cuppu, Vinodh, Jacob, Bruce, Davis, Brian, Mudge, Trevor
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study...
A Performance Comparison of Contemporary DRAM Architectures (1999)
Cuppu, Vinodh, Jacob, Bruce, Davis, Brian, Mudge, Trevor
In response to the growing gap between memory access time and processor speed, DRAM manufacturers have created several new DRAM architectures. This paper presents a simulation-based performance study...
Looking to Parallel Algorithms for ILP and Decentralization (1998)
Berkovich, Efraim, Jacob, Bruce, Nuzman, Joseph, Vishkin, Uzi
We introduce explicit multi-threading (XMT), a decentralized architecture that exploits fine-grained SPMD-style programming; a SPMD program can translate directly to MIPS assembly language using...
Looking to Parallel Algorithms for ILP and Decentralization (1998)
Berkovich, Efraim, Jacob, Bruce, Nuzman, Joseph, Vishkin, Uzi
We introduce explicit multi-threading (XMT), a decentralized architecture that exploits fine-grained SPMD-style programming; a SPMD program can translate directly to MIPS assembly language using...
Virtual Memory: Issues of Implementation (1998)
The authors introduce basic virtual-memory technologies and then compare memory-management designs in three commercial microarchitectures. They show the diversity of virtual-memory support and, by...
Virtual Memory: Issues of Implementation (1998)
The authors introduce basic virtual-memory technologies and then compare memory-management designs in three commercial microarchitectures. They show the diversity of virtual-memory support and, by...
Notes on Calculating Computer Performance (1998)
This report explains what it means to characterize the performance of a computer, and which methods are appropriate and inappropriate for the task. The most widely used metric is the performance on...
The Trading Function in Action (1998)
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
Virtual Memory in Contemporary Microprocessors (1998)
THIS SURVEY OF SIX COMMERCIAL MEMORY-MANAGEMENT DESIGNS DESCRIBES HOW EACH PROCESSOR ARCHITECTURE SUPPORTS THE COMMON FEATURES OF VIRTUAL MEMORY: ADDRESS SPACE PROTECTION, SHARED MEMORY, AND LARGE...
Virtual Memory in Contemporary Microprocessors (1998)
THIS SURVEY OF SIX COMMERCIAL MEMORY-MANAGEMENT DESIGNS DESCRIBES HOW EACH PROCESSOR ARCHITECTURE SUPPORTS THE COMMON FEATURES OF VIRTUAL MEMORY: ADDRESS SPACE PROTECTION, SHARED MEMORY, AND LARGE...
Segmented Addressing Solves the Virtual Cache Synonym Problem (1997)
If one is interested solely in processor speed, one must use virtually indexed caches. The traditional purported weakness of virtual caches is their inability to support shared memory. Many...
Segmented Addressing Solves the Virtual Cache Synonym Problem (1997)
If one is interested solely in processor speed, one must use virtually indexed caches. The traditional purported weakness of virtual caches is their inability to support shared memory. Many...
The Trading Function in Action (1997)
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
Support for Nomadism in a Global Environment (1997)
. The goal of nomadic computing transcends simply making one's environment portable; mobile users require the ability to communicate with local servers despite location and to obtain local services...
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
Software-Managed Address Translation (1997)
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple...
Software-Managed Address Translation (1997)
In this paper we explore software-managed address translation. The purpose of the study is to specify the memory management design for a high clock-rate PowerPC implementation in which a simple...
Algorithmic Composition as a Model of Creativity (1996)
There are two distinct types of creativity: the flash out of the blue (inspiration? genius?), and the process of incremental revisions (hard work). Not only are we years away from modeling the...
Algorithmic Composition as a Model of Creativity (1996)
There are two distinct types of creativity: the flash out of the blue (inspiration? genius?), and the process of incremental revisions (hard work). Not only are we years away from modeling the...
An Analytical Model for Designing Memory Hierarchies (1996)
Jacob, Bruce, Chen, Peter M., Silverman, Seth R., Mudge, Trevor N.
Memory hierarchies have long been studied by many means: system building, trace-driven simulation, and mathematical analysis. Yet little help is available for the system designer wishing to quickly...
Support for Nomadism in a Global Environment (1996)
The goal of nomadic computing transcends simply making one's environment portable; mobile users require the ability to communicate with local servers despite location and to obtain local services...
The Trading Function in Action (1996)
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
The Trading Function in Action (1996)
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
This paper describes a commercial software and hardware platform for telecommunications and multimedia processing. The software architecture loosely follows the CORBA and ODP standards of distributed...
Memory Management Hardware, and its Support for Operating Systems (1996)
. This survey compares and contrasts the memory management designs of six commercial microarchitectures in the context of today's operating system requirements, which include such features as...
Composing With Genetic Algorithms (1995)
Presented is an application of genetic algorithms to the problem of composing music, in which GAs are used to produce a set of data filters that identify acceptable material from the output of a...
Composing With Genetic Algorithms (1995)
Presented is an application of genetic algorithms to the problem of composing music, in which GAs are used to produce a set of data filters that identify acceptable material from the output of a...
Thesis (M.S. in M.E.)--Georgia Institute of Technology, 1988. Directed by Jonathan Colton.